1. Field of the Invention
This invention relates to parasitic capacitance in multilayer printed circuit boards and in particular to the reduction of parasitic capacitance in interconnection modules.
2. Description of the Related Art
In many communication systems electrical communication signals are conveyed between various equipment used in such systems. Typically, the electrical signals can be interconnected and routed to various equipment located at a central office. The interconnection and routing of the electrical signals are implemented with interconnection modules, some of which are called Digital Distributing Frames (DDF).
In a central office which may contain various communication equipment, a plurality of DDF modules are typically disposed in a housing. Typically, a DDF module comprises several connectors (e.g., BNC connectors) with electrical connections substantially perpendicular to a printed circuit board of a certain thickness which contains electrical ground planes and circuit traces (i.e., etched conductors) that connect the appropriate sets of the mounted connectors.
Referring to FIG. 1, there is shown a side view of a portion of a DDF module. Connector 100 is mounted to a printed circuit board having three layers 102, 104 and 106. The layers are typically made from insulating material having a certain dielectric constant. A conductor 108 is etched or plated onto layer 104 and connected to plated through hole 110. Connector 100 has mounting pins 114 that are inserted into mounting holes 116. Connector 100 has center conductor 112 which is electrically connected to conductor 108 via plated through hole 110. Center conductor 112 extends through plated through hole (or via) 110 past conductor 108 and extends through the remaining depth of the printed circuit board. The portion of center conductor 112 that extends past conductor 108 creates a parasitic effect on conductor 108 and on circuits connected to conductor 108.
A parasitic effect is the creation of extraneous circuit elements (e.g., capacitance, inductance) resulting from the particular geometry of conductors and insulating material associated with a circuit. The parasitic effect associated with center conductor 112 tends to be a parasitic capacitance. Such a parasitic capacitance can distort electrical signals carried by center conductor 112 and effect adversely the performance of circuits connected to central conductor 112. The extent of the effect on circuit performance and signals depends on the value of the parasitic capacitance. The value of the parasitic capacitance is determined in part by the length of center conductor 112, the diameter of center conductor 1 12 and the dielectric constant of the material surrounding the part of center conductor 112 extending past conductor 108.
Therefore, there is a need to reduce the parasitic effects resulting from the geometry of a printed circuit board and the conductors inserted therein.